Course content:

Fundamental concepts in Digital Abstraction, MOSFET switch, CMOS basics, Digital Circuit speed, NMOS logic, CMOS logic, combinational logic, sequential logic, synchronous sequential design,

timing awareness, setup/hold requirement significance, asynchronous circuits, metastability, synchronization, logic synthesis fundamentals, advanced logic synthesis (PLE based), floor planning, place & route, clock tree synthesis, signal integrity, IR-drop analysis, Static Timing Analysis, low power design techniques etc. And one mini project, two major projects.

PHASE 1

Introduction to VLSI Basics

  • Fundamental concept of MOSFET and CMOS operations
  • Basic digital circuit and layout
  • Introduction to fabrication technologies
  • CMOS fabrication

PHASE 2

Input to Physical Design

  • Library files
  • Technological files
  • Netlist
  • IO constraints
  • Synopsys Design Constraints
  • Different EDA tools and its file formats

PHASE 3

Partitioning

  • Why partitioning?
  • Design Partitioning and its advantage
  • Different type of partitioning
  • Methods of partitioning
  • Partitioning based upon Logical Groups
  • Partitioning based on Clock Groups

PHASE 4

Floor planning

  • Why floor planning?
  • Goal of floor planning
  • Floor planning based on I/O Constraints File
  • Aspect ratio
  • I/O Cora Clearance
  • Flip, Abut
  • Double back
  • Congestion Analysis

PHASE 5

Power Planning

  • Why Power Planning
  • Various Methods
  • Power mesh
  • Core Power Rings
  • Macro Power Rings
  • Straps and Trunks

PHASE 6

Placement

  • What is Placement/Goals & Objectives
  • Basics of Placement
  • Inputs / Outputs
  • Placement Flow / Placement steps
  • Placement Constraints
  • Pre place optimization
  • HFN synthesis
  • In placement
  • Search and refine
  • Post placement optimization before CTS Re synthesis
  • Fix Setup, Fix Hold
  • Scan Chain
  • Issue with the Scan chain
  • Solution to the scan chain
  • Issue in Placement
  • Optimization Technique
  • Final checks

PHASE 7

Clock Tree Synthesis

  • What is CTS, Goals & Objectives?
  • Objective of CTS
  • Inputs / Outputs
  • Optimization procedure
  • Buffer sizing
  • Relocation
  • Fix Hold
  • Post Placement optimization after CTS

PHASE 8

Routing

  • What is Routing?
  • Different types of Routing
  • Timing Driven Routing
  • Congestion driven Routing
  • Net Constraints
  • Global Routing
  • Track Assignment
  • Detail Routing
  • Search and refine
  • Post Route Optimization

PHASE 9

Signal integrity

  • SI Analysis
  • Cross talk delay
  • Glitch analysis
  • IR Drop
  • Electro migration
  • Ground Bounce
  • Antenna Violations

PHASE 10

Timing

  • Why Timing Analysis
  • What is STA?
  • Pros & Cons of STA
  • Performing Analysis
  • Timing Verification & Corners
  • Setup & Hold Timing
  • Estimating RC values
  • Wire load Models
  • Net and Cell Delay Calculations
  • Clock Skew
  • Timing path and arcs
  • Constraints
  • Source and Network Latency
  • Jitter
  • Hold check
  • I/O Constraints
  • Input and Output delay

PHASE 11

Physical Verification

  • Post Layout Verification
  • DRC
  • ERC
  • LVS
  • LPE/PRE

LINUX: User level