This course will provide you the detail of Verilog language. Verilog is a HDL language i.e. Hardware Description Language which is to be widely used for modeling and functional simulation of Digital Circuits. Verilog training module emphasizes on deep understanding of concepts in Verilog.

The course is organized into module and phases which include Lectures, Videos, PPTs, and Hands-On Labs. And finally gets completed with an Industry standard project

Course Highlights:

• Avoid the common mistakes people make when they are first using Verilog
• modeling combinational and sequential hardware blocks
• Specially how to use blocking/non-blocking assignments.
• Direct and Random test-benches to verify your RTL code
• Synthesizable RTL design descriptions
• How to use function and task in Verilog

Structure Content

Module 1:- Introduction to vlsi design
• Evolution of vlsi system
• Application of VLSI system
• ASIC Design flow
• Role of HDL

Module 2:- Introduction to Verilog
• Need of Verilog
• Abstraction levels
• Concurrency
• Digital circuit designing with Verilog
• Need of verification of HDL design
• Simulation and Synthesis
• Testbench
• 4-state logic

Module 3:- Verilog Syntax and Semantics
• Keywords
• Identifiers
• White spaces
• Comments
• Numbers representation
• Data Types
• Scalar and Vectors
• Operators
• Delays

Module 4:- Gate Level Modeling
• Introduction to gate level modeling
• How to construct a module
• Design of gate primitives
• Design of Half Adder
• Design of Multiplexer at Gate level
• Modeling of tri-state gate
• Design of basic digital design at gate level

Module 5:- Data flow modeling
• Introduction to Data flow modeling
• Continuous assignment structures
• Assignment statements and their use
• Designing with testbenches
• Digital circuit design using continuous assignments

Module 6:- Behavioral Level modeling-I
• Introduction to behavioral modeling
• Procedural blocks
• Design with multiple always blocks
• Blocking and Non-blocking assignments
• if-else construct
• Case statement
• Introduction to loops
• Designing with for, repeat, while and forever loop
• Digital circuit designing at behavioral level

Module 7:- Behavioral Level modeling-II
• Advanced circuit designing at behavioral level
• System Tasks
• Tasks and Functions
• Introduction to FSM
• FSM circuit designing

Module 7:- Memory Designing
• Introduction to memory designing
• Dual Address ROM design
• Single Address RAM design
• Designing of FIFO