1. Sleepy Keeper Approach for Power Performance Tuning in VLSI Design.
2. Adiabatic Logic Based Low Power Multiplexer and De-multiplexer.
3. Low Power D-latch design using MCML Tri-state Buffers.
4. Low power adiabatic booth multiplier using Positive feedback adiabatic logic (PFAL).
5. Clock gated 4-bit Johnson counter using low power JK flip flop.
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