1. Implementation of pipe lined AES algorithm on FPGA (Xilinx) kit.
2. Image compression technique with discrete wavelete transform technique applied by Verilog for the efficient use of area.
3. Verilog implementation of RSA cryptography algorithm.
4. FPGA implementation JPEG 2000 using 2-D DWT .
5. FPGA implementation of the 12-bit Ternary multiplier.

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