Technology Scaling in Electronic Circuits

In this highly advanced and competitive era of technology, portability and compactness of electronic devices is required along with its being fully featured. Research titans like Intel, Texas Instrument and IBM are proposing their work of chip implementation at around 7 nm these days. The certain need of reducing the device size arises due to following requirements of an electronic device:

Verification and testing is the most crucial step of chip designing process in VLSI industry.


Extraction of all the parasitic information from the design is the first step in full-chip verification. The extraction of signal and power nets is followed by analysis of all the transistors must be done for potential problems.

There are some full chip verification techniques which are as follows:


Charge recycling technique for digital circuits play vital role for decreasing the power. In this digital prominent era, Ample of researches are going on for diminishing power. MTCMOS circuits selectively connect/disconnect the low threshold voltage logic gates to the power supply or the leakage current produced by an MTCMOS circuit is significantly less. MTCMOS (Multi Threshold CMOS) technology provides a solution to the low power design requirements but with this boon of low power technique (MTCMOS) there is a problem of significant power dissipation during mode transition i.e. the active-to-sleep or sleep-to-active mode transitions consume a significant amount of additional energy in the conventional MTCMOS circuits.