Introduction:

          The need for low power techniques are increasing day by day, because portable devices are dominating the today’s electronics market. To meet the power requirements of the portable devices, we have to increase the specific weight of the batteries in the portable devices according to the technology scaling in the devises. But the growth in the specific weight of the batteries is not that much rapid as compared to the technology scaling and also the specific weight of the batteries is already reached to the chemical explosive level. So increasing the specific weight of the batteries is not that much safe to the users and as well as to the environment. The alternative is to reduce the power consumption in the CMOS circuits.

            Now a days we are following a lot of techniques to reduce the power consumption in the CMOS circuits. One of the techniques is reducing the power supplies in the circuits, because the power consumption is directly proportional to the square of the supply voltage in the circuit. To make the circuit properly operate even after reducing the supply voltages we have to scale down the MOSFET parameters accordingly. If we scale down the technology below 60nm the effect of leakage current will become significant and dominates the power consumption in the circuits. Basically the leakage current in the CMOS circuits is very less and negligible. But as the technology scales down below 60nm, the second order effect which is called sub-threshold leakage current will come into picture and dominates the power consumption. To reduce this leakage current one of the best technique is using the sleep transistors in with high threshold voltage Vth_high to control the leakage power. This technique is called “POWER-GATING” or “MULTIPLE THRESHOLD CMOS TECHNIQUE”. This technique is shown in below fig:1

Sleep Transistor Technique

              In the above technique because of the two sleep transistors the output voltage levels will be degraded due to voltage drops across the sleep transistors, and it also reduces the noise margin of the circuits. So to avoid that we will use only one transistor, either footer sleep transistor or header sleep transistor, as shown in below figure2.

with header and footer sleep transistors

            In the above circuit the sleep transistors are off in sleep mode and because of their less leakage property they won’t allow more current to leak through them and controls the amount of current flowing through them. But the drawback in the above technique is sleep to active wakeup time is large. It is because in the sleep mode all the internal nodes of the circuit with footer NMOS sleep transistor will be charged to almost Vdd and similarly all the internal nodes in the logic circuit with header PMOS sleep transistor will be discharged to 0V. So the node capacitance at the drain of the NMOS sleep transistor will also be charged to Vdd and the node capacitance at the drain of the PMOS header sleep transistor will be discharged to 0V. So when sleep to active transition is occur, the drain capacitance of the NMOS sleep transistor has to be discharged from Vdd to 0V and similarly the node capacitance at the drain of the PMOS sleep transistor has to be charged from 0V to Vdd. The charging and discharging of the internal node capacitances take time to bring the circuit into active mode. This limits the operating speed of the circuit. One more disadvantage in this circuit is that the charge consumed during the charging and discharging of these internal parasitic node capacitances is going to be wasted. During the active-sleep and sleep-active mode transitions the node capacitance has to be either charged from 0V to Vdd or discharged from Vdd to 0V. To reduce this wastage of energy dissipation during the mode transition the best technique is charge sharing between the drain capacitance of the NMOS sleep transistor and the drain capacitance of the PMOS sleep transistor. We can do this charge sharing immediately before and after the active mode. The charge sharing between these nodes can be achieved as shown in below fig3.

sharing between the node capacitances

In the above circuit C1 and C2 represents the logic blocks, SN and SP represents the NMOS sleep transistor and PMOS sleep transistor. CG and CP represents the node capacitances at the drain terminals of the NMOS and PMOS sleep transistors respectively. During the active mode the voltage drops across CG and CP are 0V and Vdd respectively. When the sleep signal is applied CG will try to charge to Vdd and CP will try to discharge to 0V. If we close the switch represented by M immediately after sleep signal is applied for a short duration of the time the charge stored in the capacitor CP will be shared with the capacitance CG. For example let us consider that both the capacitances are equal that is CG=CP. So the charge stored in the capacitor CP in the active mode will be equally shared between the CG and CP. Then the voltage across the two capacitors after charge sharing is equal to Vdd/2. so the capacitor CG only need to charge from Vdd/2 to Vdd and the capacitor CP needs to discharge only from Vdd/2 to Vdd. So by sharing charge between two capacitors we are going to reduce half of the mode transition energy which is going to be wasted during active to sleep mode transition. Applying similar process immediately before sleep to active mode transition by closing the switch M for a short duration of the time we will reduce the charge that is going to be wasted during the sleep to active mode transition. So by using this technique we can save maximum of 50% of the wastage of the charge during the mode transition in CMOS circuits. One more advantage of the charge recycling is the sleep to active wake up time will also be reduced because now the capacitors are only needed to either charge from Vdd/2 to Vdd or Vdd/2 to 0V. So the operating speed of the circuit is also going to be increased.

Advantages:

  1. Reduction in wastage of energy during mode transition.
  2. Operating speed increases